The vertical cavity surface emitting laser is a semiconductor laser that emits light perpendicular to the substrate, in contrast to the conventional edge emitting laser. VCSELs have several advantages compared to conventional edge emitting semiconductor lasers, which makes them very attractive for applications such as spectroscopy, data communication or consumer electronics, like DVD players. Among others, VCSEL devices provide a high power conversion efficiency, low threshold currents (less than 1 mA is possible), better focusing due to a symmetrical circular beam profile, ability to test devices on wafer, ease of fabrication into arrays, high temperature stability and high reliability.
The key design of a VCSEL device comprises two mirrors which are stacked on top of each other parallel to a substrate. The mirrors are stacks of alternating semiconductor layers of different indices of refraction which are designed to form distributed Bragg reflectors. The two mirrors are doped with n-dopants and p-dopants, respectively, such that an interface region where the mirrors contact an active region can form a p-n junction. This p-n junction defines the light emitting active area where electrons and holes can recombine causing the emission of light. The efficiency of this recombination in the active area can be improved by using a heterostructure with sufficiently thin layers in the active layer which can form so-called quantum wells. A basic structure thereof is described, for example, in U.S. Pat. No. 4,949,350.
In a typical configuration, each mirror comprises of a periodic layer stack of up to 40 alternating low and high refractive index AlxGal1-xAs layers , whereby each layer has a thickness corresponding to the optical length of λ/4, wherein λ is the wavelength of the emitted laser light. Thus reflectivities as high as 99.99% can be achieved . One of the mirrors is provided with lower reflectivity thereby defining an output coupler for the emission of laser radiation. Together with a high efficiency of the active region this results in a low threshold current of only a few mA.
A further advantage of the VCSEL is that it enables a single mode design. The selection of a single longitudinal mode can be achieved by a thin cavity in the range of a wavelength of the desired mode. Moreover, a lateral optical confinement to a few microns is important to enable emission in a narrow beam. This may be achieved by lateral structuring of at least one mirror. Substantially this method is called lateral index guiding. A possibility to accomplish lateral index guiding is to shape the upper mirror as circular pillar or taper. This can be fulfilled for example by removing material of a flat distributed Bragg reflector apart from a circular region by employing a wet chemical or dry etch process, which results in a so called mesa structure. The lateral waveguide normally supports multi-transverse mode operation. However, by introducing additional mode filtering structures the losses of the higher order modes can be enhanced relative to the fundamental mode so that the laser device can operate in single mode. A single-mode VCSEL design and a method of its fabrication according to the foregoing is described for instance in EP 1035621.
Triggered by the enormous increase in data rates in local area networks, there has been a strong focus on the development of high speed VCSELs for data transmission applications in recent years. Today, fiber based optical transceivers using oxide confined short wavelength VCSELs with data rates up to 2.5 Gb/s are already commercially available. New local area network communication standards for higher data rates, however, are currently being developed (e.g., 10-Gigabit Ethernet) and will shortly require even faster VCSELs and VCSEL arrays.
A critical factor that limits the maximum modulation speed of VCSELs is the influence of parasitic capacitance caused by electrical parasitic device components which surround the active region of the laser. Most important in this respect is the parasitic capacitance of the bond pads, since it gives rise to a high frequency shunt path around the active laser region. The bond pad capacitance normally dominates, but there are additional minor capacitance contributions due to a possible oxidation layer and the laser diode junction. Moreover, in the case of VCSEL arrays with one common contact of the individual array devices, a high bond pad capacitance leads to a high frequency cross talk resulting in signal distortions.
There are different approaches to optimize the VCSELs for low bond pad capacitance, which have their specific advantages and disadvantages. K. M. Geib et al. summarizes different approaches in “Comparison of Fabrication Approaches for Selectively Oxidized VCSEL Arrays,” Proc. SPIE, vol. 3946, pp. 36–40, 2000. There are roughly two categories depending on whether the VCSEL epitaxial layer structure is grown on a doped or a semi-insulating substrate.
In case of a doped substrate, the conductive substrate is typically metallized on the backside to provide the contact for the bottom mirror and only one bond pad is evaporated on the top epitaxial side of the wafer to provide the contact for the top mirror. Due to the wire bonding, the size of the bond pads cannot be arbitrarily reduced and is typically around 100 μm×100 μm. To minimize the capacitance, these devices, therefore, require isolation layers with low dielectric constant and several micron thickness. The etched area around the VCSEL mesa is often completely filled with a polymer (e.g. polyimide, BCB) to get a planarized structure. Such devices are simple to fabricate and several groups have demonstrated prototypes with record high modulation bandwidths.
Unfortunately, polymer planarization is reported to result in voids at the mesa/polymer interface which can lead to breaks in the metal line connecting the mesa to its bond pad. Another significant drawback is the weak metal adhesion to the polymer, which often results in bonding failures due to a delamination of the bond pad.
In the case of a semi-insulating substrate, the known device structure uses an additional contact on the same side of the semi-insulating wafer with regard to the top mirror contact, to allow the injection of charge carriers into the light emitting active region from the bottom mirror side. Etching through the semiconductor layers down to the semi-insulating substrate allows the placement of bond pads for both contacts, the bottom mirror contact and the top mirror contact, close to the level of the semi-insulating substrate. Conductive layers connect the bond pads either with the bottom mirror or the top mirror. A spatial separation of both bond pads removes most of the bond pad capacitance. Thick isolation layers are not needed for a capacitance reduction, but a polymer is often used to bridge the large height difference between the mesa top and the substrate. Hence, this design combines good bond pad adhesion with low capacitance.
Very challenging parts of this approach, however, are the lithographic steps for the metallization over the large height differences (around 10 μm) from the mesa top to the substrate. For typical metal lift off processes, the photoresist has to be structured over both height levels, so that very thick photoresists are required which is at the expense of the lithographic fidelity and process stability. Hence, this device structure has great potential due to the low capacitance, but a reliable fabrication sequence is required to be suitable for production purposes.
In a classical approach, as it is exemplified in U.S. Pat. No. 4,949,350, the stack of semiconductor layers comprising the bottom mirror and the top mirror is placed on a layer of conductive material which may be laminated on the substrate. After removing of layer material around the mesa by etching, the surface of the layer of conductive material is freely exposed and the bottom mirror and the top mirror can be contacted via wire bonding to conductive layers on the substrate and the top of the mesa.
Wire bonding, however, suffers from high parasitic capacitance due to the thin and relatively long bonding wires.
U.S. Pat. No. 5,468,656 describes a VCSEL wherein the mesa is formed by etching a moat. The top mirror is contacted by a conductive layer which extends from the top of the mesa across the moat to a contact pad. To avoid large height differences the moat is etched only partly into the top mirror. To confine the charge carriers to the mesa region and to avoid shunt paths for the charge carriers the material beneath the ground of the moat is treated with implantation techniques to disrupt conductivity from the mesa region to adjacent regions. Apart from the mesa an opening is etched through the top mirror and the light emitting active region down to the bottom mirror. A layer of conductive material on the ground of the opening serves as contact pad for contacting the bottom mirror.
Although this solution provides a moderate separation of contact pads this disclosure leaves the problem of bridging the height difference to the chip surface for an interconnection to the contact pad of the bottom mirror.
Another approach to reduce parasitic capacitance is described in EP 1073171-A2 utilizing lateral injection of charge carriers. A lateral injection VCSEL comprises upper and lower mirrors forming a cavity resonator, an active region disposed in the resonator, high conductivity upper and lower contact layers located on opposite sides of the active region, upper and lower electrodes disposed on the upper and lower contact layers, respectively, and on laterally opposite sides of the upper mirror, and a current guide structure including an apertured high resistivity layer for constraining current to flow in a relatively narrow channel through the active region, characterized in that a portion of the lower contact layer that extends under the top electrode has relatively high resistivity. This feature of EP1073171 serves two purposes. First, it suppresses current flow in parallel paths and, therefore, tends to make the current density distribution in the aperture more favorable for the fundamental mode. Second, it reduces parasitic capacitance.
This structure, however has still the disadvantage that the contact layers are on different levels and a high capacitive bonding technology has to be used for the interconnection of upper and lower contacts.
An approach to improve performance and speed of a VCSEL is described in EP 0663112 wherein a reduction of a serial resistance is achieved by intra cavity structures. The intra cavity structures are formed by a stratified electrode disposed substantially between the light emitting active region and the top mirror. The stratified electrode comprises a plurality of alternating high and low doped layers having a first conductivity type for injecting current into the light emitting active region to cause lasing, thereby establishing a standing wave in the cavity.
WO 01/04951 A1 describes a low capacitance bond pad for high speed VCSEL devices. In the VCSEL described therein, a metal contact area, an associated metal bonding pad and an interconnecting metal bridge are disposed on top of a conductive upper mirror stack. To prevent current flow from the pad through the conductive mirror stack which would bypass the active medium, a moat is etched surrounding the pad area. The moat isolates the pad area and the conductive material beneath the pad area. The metal contact area for the bottom mirror stack is located on a second level. It is, however, difficult to insure reliable fabrication and packaging.